[Optical lithography]
[Etching holes in the wafer]
[Filling up the holes]
[Removing the resist]
[Optional sputtering of a protection layer]
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All samples in this thesis, which are used for manipulation or positioning of magnetic markers, have the same basic preparation procedure. Figure 3.1 presents the five main steps in the procedure. The first step is the optical lithography (a) that consist of spin-coating the sample with a resist, exposing it with a laser lithographer, and developing the resist to get the written design (check section 2.3 for a comprehensive description of optical lithography). Then, the whole sample is etched with Ar-ions, so 200nm deep holes are created where the resist was removed (b) (see section 2.2 for a description of the etching process). These holes are exactly filled up with Au (c), using 5nm thick Ta below and on top as an adhesive agent (thin grey layers). Finally, the resist is removed (d), and optionally, a protection layer of 100nm SiO is sputtered onto the sample (e).
Initially, the conducting lines were not embedded into the Si-wafer, but first experiments showed that the protruding lines are real obstacles for the magnetic particles. This is no real surprise, as the height of the conducting lines is nearly one third of the diameter of a bead. Because the conductivity of gold is much higher than the conductivity of silicon, it is no problem to embed the gold lines into the Si-wafer (confer figure 3.1c).
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The SiO protection layer is not added for all experiments, as it is only imperative for the bond-force measurements. But this layer helped in several experiments and was used in many cases.
The thickness of the conducting line and the width at the narrowest point determines the resistance and the maximum possible current. In most samples the resistance of a conducting line is between 20 and 300 and the maximal possible current is about 30 to 150mA.
For most measurements, the sample is glued with conductive silver paste to an IC-socket. For an easy connection, the contact pads of the structure are then wire bonded to the IC-socket. Figure 3.2 shows a complete sample in the IC-socket.